1. Field of the Invention
The present invention relates to package stack devices and fabrication methods thereof, and more particularly, to a package stack device having a plurality of package structures stacked on each other and a fabrication method thereof.
2. Description of Related Art
Along with the development of semiconductor packaging technology, various types of packages haven been developed for semiconductor devices. In order to further enhance electrical performance and reduce package size, a plurality of package structures are stacked on each other to form a POP (package on package) device. As such, electronic elements having difference functions, such as memories, CPUs (central processing units), GPUs (graphics processing units), image application processors and the like, can be integrated together so as to be applied in various kinds of thin-type electronic products. FIG. 1 schematically illustrates a cross-sectional view of a conventional package stack device.
Referring to FIG. 1, a second package structure 1b is stacked on a first package structure 1a. The first package structure 1a comprises a first substrate 11 having a first surface 11a and a second surface 11b opposite to the first surface 11a, and a first electronic element 10 disposed on the first surface 11a and electrically connected to the first substrate 11. The second package structure 1b comprises a second substrate 12 having a third surface 12a and a fourth surface 12b opposite to the third surface 12a, and a second electronic element 15 disposed on the third surface 12a and electrically connected to the second substrate 12. Further, a plurality of solder balls 110 are formed on the first surface 11a of the first substrate 11 so as for the fourth surface 12b of the second substrate 12 to be stacked thereon and electrically connected to the first substrate 11. Furthermore, a plurality of ball pads 112 are formed on the second surface 11b of the first substrate 11 for mounting solder balls 14. The first and second electronic elements 10, 15, which can be active components and/or passive components, are flip-chip electrically connected to the substrates 11, 12, respectively, and an underfill 13 is filled between the electronic elements 10, 15 and the substrates 11, 12 so as to bond the electronic elements 10, 15 with the substrates 11, 12, respectively.
However, since the second package structure 1b is stacked on the first package structure 1a through a soldering process, the solder material forming the solder balls 110 can easily contaminate surfaces of the first and second package structures 1a, 1b during reflow. Further, variation in the size of the solder balls 110 is not easy to control, which can easily adversely affect vertical stacking of the two package structures and even cause positional deviation of joints between the two package structures.
Furthermore, with the increase of stack height, the diameters of the solder balls 110 must be increased. Accordingly, the area of the surfaces (the first surface 11a and the fourth surface 12b) occupied by the solder balls 110 is increased. Consequently, the spaces available for the electronic elements and circuits are reduced.
Moreover, increased size of the solder balls 110 can easily cause bridging between the solder balls, thus adversely affecting the product yield.
In addition, since the second package structure 1b is supported by the solder balls 110 on the first package structure 1a and a big gap exists between the first and second package structures 1a, 1b, warpage can easily occur to the first and second substrates 11, 12.
Therefore, there is a need to provide a package stack device and a fabrication method thereof so as to overcome the above-described drawbacks.